Digital IC Verification Engineer (17006)

Měsíčně:120 000 CZK
Místo:Praha, Brno
Začátek:2/2020, Délka: HPP
Home office:neuvedeno
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Are you experienced verification engineer with ambition to participate on development of state-of-the-art designs? Are you ready for challenges of ultra-low power, low voltage integrated circuits for battery-operated and field-powered applications?
If so, our client would like to offer you the opportunity to be part of their digital and mixed-signal design verification team.

Nástup: ASAP
Forma spolupráce: HPP
Lokalita: BRNO

Project description:
You will have the opportunity to be part of digital/mixed-signal design verification team and to work on the true ultra-low power designs verification.

As part of our digital/mixed-signal design verification team you would be responsible for:
-project verification strategy and creation of UVM testbench Framework
-developmpent of behavioral models
-perform verification state-of-the-art ultra-low power digital design using UVM methodology (SystemVerilog)
-drive improvements in company verification methodologies and environment
-manage the team of young digital verification engineers
-cooperate with other company sites in US and Switzerland to improve synergy on methodology and share best verification practices
-generate the industrial test patterns

-At least 3 years experience with digital verification methodologies of integrated circuits
-Experience with building testbenches based on UVM methodology System Verilog (class approach)
-Experience with Object Oriented Programming
-Experience with TCL or Perl scripting
-Knowledge of VHDL language
-Knowledge of all digital verification steps (RTL, gate level)
-Written and fluent English
-Autonomy in his field and capability to work in multinational team

Nice to have:
-Understanding of wireless systems and communication protocols (HF, UHF, Bluetooth) would be benefitting
-Experience with Cadence verification tools
-Experience with vManager tool will be plus
-Knowledge of Formal verification