Digital IC Verification Engineer (18905)

Praha, Brno
HPP Klient
110 000 CZK
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We’re offering an excellent opportunity for an IC Verification Engineer – Senior. Our client is a company involved in the design of the most advanced low-power and low-voltage analog-to-digital integrated circuits. They also newly design embedded SW and collaborate on the development of various mobile applications with wireless communication and information systems.
Location: Praha, Brno
Form of cooperation: permanent placement
Start of cooperation: 12/2019
What will you be working on:
- definition of the physical constraints of implemented block
- update and correction of timing constraints (provide feedback to designers)
- floorplan construction, logic placement
- clock tree synthesis
- timing optimization and static timing analysis
- power consumption and IR drop analysis
- physical verification (DRC, LVS)
- Engineering Change Orders (ECO) implementation
- communication with EDA and tool vendors to fix bugs, suggest enhancements
- development of internal back-end environment
What you need to know:
- master's degree in Electrical Engineering
- having the following knowledge and experience would be a plus: logic synthesis, formal verfication
- at least 3 years of experience with digital backend tasks
- experience of all IC place & route steps: from floorplanning to physical verification
- experience of Static Timing Analysis (STA)
- experience with multi-level domain digital design (UPF definition)
- knowledge of TCL or Perl/Pyhton scripting
- written and spoken English on a good level
- competitive salary including benefits
- flexible working hours
- a role in a dynamic and multi-cultural team where everyone can make a difference
- access to the state-of-the-art and innovative digital backend methodology and tools
- opportunity to bring your experience and ideas to the table
- team atmosphere
- technical and soft-skill trainings
- international work environment with teams in Switzerland and US
- traveling opportunities